1. Field
This patent specification relates to an optical disk apparatus in use for recordable optical media such as CD-R, CD-RW and other similar media, and more particularly, to techniques of generating standard clock signals for properly timing the data recording.
2. Discussion of the Background
In optical disk apparatuses in use for recordable optical media such as a Compact Disk-Recordable (CD-R), CD-Recordable (CD-RW), for example, data recording is carried out in a predetermined data format, in which standard recording clock signals (or standard clock signals for data recording) are utilized, that are formed synchronous with standard clock signals. The standard clock signals, in turn, are generated on the basis of the signals from a crystal oscillator, for example.
For optical recording media such as CD-R, CD-RW, the format for data recording is specified in a book of standards, Orange Book. It has been known that, as long as the whole data recording is completed without interruption, recording can be achieved without problems with the above noted method utilizing standard recording clock signals which are formed synchronous with standard clock signals based on those from the crystal oscillator.
FIG. 5 is a block diagram illustrating the major parts of a clock signal generator previously known for generating standard clock signals for data recording.
Referring to FIG. 5, a clock signal generator 100 comprises a phase locked loop (PLL) circuit which is configured to detect the differences in both frequency and phase between the following two signals by means of a frequency and phase detector (PFD) 104 so as to control a voltage control oscillator (VCO) 102; a first signal being generated based on 33.8688 MHz clock signal, which is output from a crystal oscillator (not shown) and then input to CLKIN terminal, having a frequency divided by 1/48 by a 1/48 divider 101, and a second signal output from the VCO 102 and then divided by 1/49 by a 1/49 divider 103.
The signal output from VCO 102, which has a frequency of 34.5744 MHz, when PLL locked, is subsequently frequency divided by 1/8 with a 1/8 divider 105, and then output as channel clock signals to serve as standard clock signals during data writing.
Incidentally, resistors 106, 107 and capacitors 108, 109, constitute a low-pass filter, and also serve as a phase compensator for carrying out phase compensation of the signals output from PFD 104 and then outputting these compensated signals to VCO 102.
Even after providing the above noted clock signal generator, there still exist problems such as, for example, so called buffer under-error, which will be described herein below.
In order to continue data recording without any interruption as indicated above, data to be recorded must be transferred from a host computer continuously with a rate the same or greater than that of data writing into optical disks. Therefore, when the data transfer from the host is interrupted for some reason, failure in data writing results, generally known as the buffer under-error.
A method is proposed in Japanese Laid-Open Patent Application No. 10-49990 to alleviate the above noted difficulty, in which data recording is intentionally halted when any interruption is foreseen, until a sufficient amount of data has been transferred from a host computer. Upon completing the transfer, the recording is resumed starting from the location on the disk that follows the location at which the previous recording was interrupted. In this method, however, the location of the restart may not necessarily coincide precisely with that of the previous interruption because of fluctuation of disk rotation, for example.
Accordingly, it is an object of the present disclosure to provide an optical disk apparatus having most, if not all, of the advantages and features of similar employed apparatuses, while eliminating at least some of the aforementioned disadvantages.
It is another object of the present disclosure to provide an optical disk apparatus provided with a clock signal generator configured to generate standard clock signals for data recording such that the location of the data recording restart following an interruption on the optical disk coincides precisely with that of finish of the previous recording.
The following brief description is a synopsis of only selected features and attributes of the present disclosure. A more complete description thereof is found below in the section entitled xe2x80x9cDescription of Preferred Embodimentsxe2x80x9d.
An optical disk apparatus in use for recordable optical disk disclosed herein includes at least a clock signal generator configured to generate standard clock signals for properly timing data recording such that the location of data recording restart following an interruption on the optical disk coincides precisely with that of finish of a previous recording.
The clock signal generator includes a voltage control oscillator for generating and then outputting a clock signal having a frequency corresponding to an input control voltage, a variable divider for frequency dividing the clock signal output from the voltage control oscillator with a dividing ratio that is variable corresponding to an input control voltage, a fixed divider for frequency dividing a standard clock signal having a predetermined frequency with a predetermined dividing ratio, a frequency and phase detector for comparing both frequency and phase between a first signal generated by being frequency divided by the fixed divider and a second signal generated by being frequency divided by the variable divider, and then outputting a control voltage corresponding to comparison results; and a dividing ratio controller for comparing both frequency and phase between frame synch signal, that are provided for each frame data on the optical disk and acquired during playback period of recorded data, and a clock signal output from the voltage control oscillator, and then controlling the variable divider to have a dividing ratio that is variable corresponding to comparison results.
In addition, the dividing ratio controller is configured to control the dividing ratio in the variable divider such that both frequency and phase of the clock signal output from the voltage control oscillator synchronize with those of the frame synch signal, and that the dividing ratio is a predetermined value when no frame synch signal is input thereinto.
The present disclosure and features and advantages thereof will be more readily apparent from the following detailed description and appended claims when taken with drawings.